GHDL simulator doesn't support vhdl attributes without error?

I wrote some vivado RTL and then added some vhdl attributes to the ports of the entity to define the interface to Xilinx Vivado tool as follows: library ieee; use ieee.std_logic_1164.all; enti

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VHDL Multi-Process

I have a problem in synchronize my code .First I tried to put All my functions in one process but to check an instruction to another it take a cycle this I don't want to be happened so I Put any ins

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I dont know why i have this red lines instead of the normal waves, i think they are corrupted somehow

Corrupted lines in the waves Im looking if there is an error in the code, but i dont see it. library ieee; use ieee.std_logic_1164.all; entity practica_1 is port (m: in std_logic_vector(1 do

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vivado block designer not updating RTL interface in block design after modifying verilog or vhdl RTL files

I would swear that vivado has a bug in that it never refreshes any interface changes made to an RTL file, verilog or vhdl, after it has been pasted into the "block design" with "add module".... Wha

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multiplexer 8x1 with 4 2x1 multiplexer& 1 4x1

the code is show multiplexer 8x1 using 2x1 and 4x1. i try this code put is show an error that say There is no default binding for component "mux8x1". (Port "I" is not on the entity) and i don't und

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validate bd_design [xilinx.com:ip_apb_bridge]axi_apb_bridge_0 APB_M slave is not mapped

In Vivado IP integrator, does anybody know how to solve this strange error mesage when trying to use Axi-APB bridge in combination with an AXI interconnect? See attached photo. After trying to vali

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Is there a vhdl function that allows me to read the time duration of the input signal?

I’m trying to build a clock using vhdl & altera de115 I want my clock to act like below When I press the button for 2 seconds, I want my clock to go in to adjust mode. The question I have : I

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Multiplier with full adder in VHDL using for generate

I am having trouble making a generic multiplier with full adder's in VHDL using FOR GENERATE. Has someome made it?

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How to generate random 24-bits samples in VHDL

I've made an I2S transmitter which send data to an I2S-breakout board. Now I have two different (2 x 2 x 24-bits) samples to send out. But I would like to have more different samples. Maybe this is

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Can FPGA Stratix 3 memory handle large amount of data?

I need to allocate an array in FPGA of 20 elements, each of size 323 bits, but don't know if my fpga memory can handle this size. I am using an FPGA Stratix 3. I hav tried looking up on the intel

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Can't infer register error when output array type as port in vhdl

I'm new to VHDL. Currenty I'm trying to read a frame of multiple bytes via UART and output them as an array to decode later. I'm using array type as the output port (or is there anything better, y

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Vivado: after Tools->Create-and-Package-New-IP what to do components.xml output?

Let's suppose you have a non-axi bus RTL core of verilog or vhdl files, and add them to your vivado project, and sucessfully compile the rtl source files using synthesis and taking care cancel and n

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How to generate signal with using DDS in VHDL?

I am beginner in the VHDL(also DSP) and I must generate signal with using DDS. I am very confused about DDS. As I understand from my professor,firstly I must do reading from lookup table and then he

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4bit register with D_flip-flop in serial

I try to do a synchronous circuit which transfers a binary number from a 4-bit register (register A) to another 4-bit register (register B) in parallel transfer mode. The registers will be implemen

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Entity returns forcing unknown “X”

My pixel_controller entity, during simulation, acts (I think) correctly but outputs wrongly, more specifically it outputs a std_logic_vector of "forcing unknowns" instead of the right bits. Termino

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